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eor e x em42am3284lba jul. 2006 www .eor ex.c o m 512mb (4m 4bank 32) double da t a ra te sdram features ? internal double-date-ra te architec ture with 2 a cce s s es p e r clo c k cy cle . ? 1.8v 0.1v vdd/vd dq ? 1.8v l v -co m s com p atibl e i/o ? burst lengt h (b/l) of 2, 4, 8, 16 ? 3 clock rea d latency ? bi-directio n a l,intermittent dat a strobe (dqs) ? all input s except dat a and dm are sam p led at the positive edge of the system clo ck. ? dat a ma sk (dm) fo r write dat a ? sequential & interleaved burst type available ? auto precha rge optio n for each b u rst accesse s ? dqs edge -aligne d with d a t a for read cycle s ? dqs cente r -align ed with dat a for w r ite cycle s ? no dll; ck to dqs is not synch r oni ze d ? deep po we r down mo de ? partial array self-refre sh (p asr ) ? auto t e mperature com p e n sate d self-refresh (tcsr) by b u ilt-in tempe r ature sen s o r ? auto refre s h and self re fresh ? 8,192 refre s h cy cle s / 64ms description the em42a m3284 lba is high spee d synchrono us grap hic ram fabricated wi th ultra high perfo rman ce cmos proce ss cont ai ning 536,870,91 2 bit s which orga nized a s 4meg words x 4 banks by 32 bit s . the 512m b ddr sdram use s a do uble dat a rate architectu re t o accompli sh high-sp eed o peratio n. the dat a p a t h internally p r efetche s mult iple bit s a nd it transfers the dat afor b o th risin g and f a lling edg e s of the s y s t em c l ock .it means the doubled dat a band wi d t h ca n be achieve d at the i/o pins. a v ailable p a ckag es:tfb g a -90b(13mm x 1 1 mm ). ordering information part no organiz ation max. fr eq package grade pb em42am32 8 4lba-75 f 16m x 32 133m hz/ d dr26 6 @cl3 tfbga-9 0b comm ercial free * eorex re serves the righ t to change p r odu ct s o r spe c ificatio n with out notice. 1/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m pin assignment 1 2 3 7 8 9 v s s d q 3 1 v s s q a v d d q d q 1 6 v d d v d d q d q 2 9 d q 3 0 b d q 1 7 d q 1 8 v s s q v s s q d q 2 7 d q 2 8 c d q 1 9 d q 2 0 v d d q v d d q d q 2 5 d q 2 6 d d q 2 1 d q 2 2 v s s q v s s q d q s 3 d q 2 4 e d q 2 3 d q s 2 v d d q v d d d m 3 n c f n c d m 2 v s s c k e c l k / c l k g / w e / c a s / r a s a 9 a 1 1 a 1 2 h / c s ba 0 ba 1 a 6 a 7 a 8 j a 1 0 a 0 a 1 a 4 d m 1 a 5 k a 2 d m 0 a 3 v s s q d q s 1 d q 8 l d q 7 d q s 0 v d d q v d d q d q 9 d q 1 0 m d q 5 d q 6 v s s q v s s q d q 1 1 d q 1 2 n d q 3 d q 4 v d d q v d d q d q 1 3 d q 1 4 p d q 1 d q 2 v s s q v s s d q 1 5 v s s q r v d d q d q 0 v d d 90ball tfbg a / (13mm x 1 1 mm x 1.2mm) 2/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m pin desc ription (simplified) pin name functio n g 2 , g 3 c l k , / c l k (sy s tem clock) clo ck in put a c tive on the positive risi ng edge ex cept for dq and dm are activ e on both ed g e of the dqs. clk and /cl k are dif f eren tial clock inp u t s. h 7 / c s (chip selec t ) /cs enable s the com m an d decode r wh e n ?l? a nd di sa ble the comm and d e c od er when ?h?.th e ne w comman d are over- loo ked whe n the comma n d decode r is disa bled but previou s operation will still contin ue. g 1 c k e (cloc k enabl e ) activates the clk wh en ?h? and de activ a tes when ?l?. whe n dea cti v ate the clo c k,cke lo w si gnifies the p o we r do wn o r self refresh m ode. j 8 ,j9,k7,k9,k1, k3 ,j 1~ j 3 ,h 1~ h3 , a0~12 (ad d res s ) ro w ad dre ss (a0 to a1 2) and calum n address (ca 0 to ca8 ) a r e multiplexed o n the same pi n. ca10 defin es auto pre c ha rge at calum n addre s s. h 8 , h 9 b a 0 , b a 1 (ba n k addre ss) select s whi c h bank i s to be active. g 9 / r a s (ro w ad dres s s t robe ) latch es row addre s se s on the posit ive rising ed ge of the clk with /ras ?l?. en able s ro w access & pre - ch arge. g 8 / c a s (column ad dress s t ro be ) latch es col u mn add r e s se s on the p o sit i ve risi ng e d g e of the clk with /cas low . enables col u mn acce ss. g 7 / w e (w ri te enabl e ) latch es col u mn add r e s se s on the p o sit i ve risi ng e d g e of the clk with /cas low . enables col u mn acce ss. l8,l2,e8,e2 d q s 0 ~ 3 (da t a input/ o utpu t) dat a inp u t s a nd output s a r e synchro n ized with both edge of dqs. k 8 , k 2 , f 8 , f 2 d m 0 ~ 3 (da t a input/ o utpu t mas k ) dm co ntrol s dat a inp u t s . d m0 co rre sp on ds to the dat a on dq0 ~ dq7. dm1 co rre sp on ds to the dat a on dq8 ~ dq 15??.. r8,p7,p8,n7, n8,m7, m8,l7,l3,m2, m 3,n2, n3,p2,p3,r2, a8,b7, b8,c7,c8, d 7 , d8,e7, e3,d2,d3, c 2 , c3,b2, b3,a2 d q 0~ 31 (da t a input/ o utpu t) dat a in put s a nd output s are multiplexed on the same pin. a9,f1,r9/ a1,f9,r1 v dd /v ss (po w e r supp ly /ground) v dd and v ss are po we r su pply pins for i n ternal circuit s . a7,b1,c9,d1, e9,l9, m1,n9,p1,r7/a3,b9, c1,d9,e1,l1,m9,n1, p9,r3 v ddq /v ssq (po w e r supp ly /ground) v ddq and v ss q are po wer supply pin s for the output bu f f ers. f 3 , f 7 n c / r f u (no conn ection/rese rv e d for future use ) this pin i s re comm end ed to be lef t no conne ction o n the device. 3/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m absolute m aximum rating symbol item rating unit s v in , v out input, output v o lt age -0.5 ~ +2.3 v v dd , v ddq powe r suppl y v o lt age -0.5 ~ +2.3 v comm ercial 0 ~ +7 0 t op operating t e mperature ra nge e x t e n d e d - 2 5 ~ + 8 5 c t st g s t orage t e m peratu r e ran ge -55 ~ +12 5 c p d powe r di ssi p a tion 1 w i os short circuit curre n t 50 ma not e : cautio n exposi ng t he devi c e to stre ss ab ove thos e li sted i n absolute m a ximum ratings co uld cau s e pe rma nent dama ge. the device is not m eant to be operate d unde r con d i t ions out side the limit s de scrib ed in the ope rational se ction of this sp e c ificatio n. exposure to ab solute maxim u m rating con d itions for extended pe riod s may af fect de vice relia bility . capacitance (v cc =1.8v 0.1v , f=1m hz, t a =2 5c) symbol paramete r min. ty p . max. unit s c clk clo ck ca p a cit a n c e 2 . 0 4 . 5 p f c i input cap a cit ance for clk, cke, address, /cs, /ras, /c as, /we, dqml, dqmu 2 . 0 4 . 5 pf c o input/output ca p a cit a n c e 3 . 5 6 . 0 pf recommended dc operating conditions (t a =0c ~70c) symbol paramete r min. ty p . max. unit s v dd powe r suppl y v o lt age 1.7 1.8 1.9 v v ddq powe r suppl y v o lt age (for i/o buf f er) 1.7 1.8 1.9 v v ih input logi c hi gh v o lt ag e 0.8* v ddq v ddq +0. 3 v v il input logi c l o w v o lt a ge -0.3 0.2*v ddq v not e : * all volt ages referred to v ss . 4/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m recommended dc operating conditions (v dd =1. 8 v 0.1v , t a =0 c ~ 70 c) max. symbol paramete r t e st conditions -75 unit s i dd1 operating cu rre nt (no t e 1 ) burs t length=2, t rc t rc (min.), i ol =0ma , one ba nk a c t i ve 8 0 m a i dd2p precharge s t andby curren t in powe r do wn mode cke v il (max.), t ck =min 1 m a i dd2n precharge s t andby curren t in non - po we r d o wn mo de cke v il (min.), t ck =min, /cs v ih (min.) input sign als are chan ged one time durin g 2 cl ks 4 m a i dd3p active s t andb y current in powe r do wn mode cke v il (max.), t ck =min 3 m a i dd3n active s t andb y current in non - po we r d o wn mo de cke v ih (min.), t ck =min, /cs v ih (min.) input sign als are chan ged one time durin g 2 cl ks 1 0 m a i dd4 operating cu rre nt (burst mode ) (n ote 2 ) t ck t ck (min.), i ol =0ma , all banks acti ve 1 2 0 m a i dd5 refre s h cu rrent (no t e 3 ) t rc t rfc (min.), all banks a c tive 9 0 m a i dd6 self refres h current cke 0.2v 0 . 8 m a *all volt ages referen c e d to v ss . not e 1: i dd1 d epen ds o n ou tput loading a nd cycl e rate s. s pecified val ues a r e obt ai ned with the output ope n. input sign als are chan ged only one time during t ck (min.) not e 2: i dd4 d epen ds o n ou tput loading a nd cycl e rate s. s pecified val ues a r e obt ai ned with the output ope n. input sign als are chan ged only one time during t ck (min.) not e 3: min. of t rfc (auto refresh ro w cycle t i me s) i s sho w n at ac characte ri stics. recommended dc operating conditions (continued) symbol paramete r t e st conditions min. ty p . max. unit s i il input lea kag e curre n t 0 v i v ddq , v ddq =v dd all other pin s not unde r tes t = 0 v - 2 + 2 u a i ol output lea ka ge cu rrent 0 v o v ddq , d out is disa bl ed - 1 . 5 + 1 . 5 u a v oh high l e vel o u tput v o lt age i o = - 0 . 1 m a 0 . 9 * v ddq v v ol low l e vel ou tput v o lt age i o = + 0 . 1 m a 0.1*v ddq v 5/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m block diagram au to / s elf re fres h c o u n t e r memory a rray s / a & i / o gating co l . de c o d e r c o l . ad d . bu ffe r mo de re g i st e r s e t co l a d d . co un te r bu rst co un te r writ e d q m co nt rol data in data out doi a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a1 0 a1 1 a1 2 ba 0 ba 1 timing reg i st er c l k c ke / c s / ra s / c a s / w e dm dm /clk dqs 6/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m ac operating t e s t conditions (v dd =1. 8 v 0.1v , t a =0 c ~70 c ) item conditions output refe rence level 0.9v/0.9v output loa d see diag ram as bel ow input signal l e vel 1.6v/0.2v t r a n sition t i me of input signal s 0.5ns input referen c e level 0.9v ac operating t e st characteristics (v dd =1. 8 v 0.1v , t a =0 c ~70 c) -7.5 symbol paramete r min. max. unit s t dqck dq outp u t acce ss from cl k,/clk 2 6 ns t dqsc k dqs output a c cess from clk,/clk 2 6 ns t cl ,t ch cl lo w/high l e vel wid t h 0.45 0.55 t ck t ck clo ck cycle t i me 7.5 ns t dh ,t ds dq an d dm h o ld/setu p time 0.8 ns t dip w dq an d dm i nput pul se wi d t h for each input 1 . 7 5 n s t hz ,t lz dat a o u t high /low imped an ce time from clk,/clk 1 6 n s t dqsq dqs- dq sk e w for a s s o ciat ed dq sign al 0 . 6 n s t dqss w r ite com m a nd to first latching dqs transitio n 0 . 7 5 1 . 2 5 t ck t dsl ,t dsh dqs input va lid wind ow 0.2 t ck t mr d mode regi ster set comm and cy cle time 2 t ck t wp r e s w r ite preamb l e setup time 0 ns t wp s t w r ite preamb l e 0.4 0.6 t ck t ih ,t is addre s s/co ntrol input hol d/setup time 1 . 3 n s t rpre rea d pream ble 0.9 1.1 t ck 7/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m ac operating t e st characteristics (continued) (v dd =1. 8 v 0.1v , t a =0 c ~70 c) -75 unit s symbol paramete r min. max. t rpst rea d post a m ble 0.4 0.6 t ck t ras active to precha rge comm and pe riod 45 120 k n s t rc active to active comma nd perio d 75 ns t rfc auto refre s h ro w cycl e t i me 108 ns t rcd active to rea d or w r ite del ay 30 ns t rp precharge co mmand p e rio d 22.5 ns t rrd active bank a to b comma nd peri od 15 ns t ccd colum n add ress to colum n address delay 1 t ck t hzp pre-cha r g e comman d to high-z 3 t ck t cdl w last dat a in to w r ite com m and 1 t ck t dpl last dat a in to precharge comm and 3 t ck t srex exit self refre s h to non -col. comma nd 16 t ck t wt r internal w r ite to read com m and d e lay 1 t ck t cke cke minimu m pulse wid t h 2 t ck t wp d w r ite to pre-charg e delay (same ban k) 3+bl/2 t ck t rpd rea d to pre - charg e delay (same ban k) bl/2 t ck t wr d w r ite to read comma nd de lay 2+bl/2 t ck t bstw burst sto p to write del ay 3 t ck t wr d w r ite recovery 2 t ck t refi a v erage p e ri odic refre s h i n terval 7.8 us 8/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m simplified s tate diagram 9/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m 1. command t r ut h t a ble cke comm and symbol n-1 n /cs /ras /cas /we ba0, ba1 a10 a12~a0 ignore comm a n d d e s l h x h x x x x x x no op eratio n nop h x l h h h x x x burs t s t op bsth h x l h h l x x x rea d read h x l h l h v l v rea d with au to pre- cha r ge reada h x l h l h v h v w r i t e w r i t h x l h l l v l v w r ite with auto pre- cha r g e wri t a h x l l h h v h v bank a c tivate act h x l l h h v v v pre-c h arge selec t bank pre h x l l h l v l x pre-cha r g e all banks p a ll h x l l h l x h x mode regi ster set mrs h x l l l l l l v h = hi gh leve l, l = low lev e l, x = high o r low level (don't ca re), v = v a lid da t a i nput 2. cke t r uth t a ble cke item comm and symbol n-1 n /cs /ras /cas /we addr . idle cbr r e fre s h comma nd ref h h l l l h x i d l e s e l f refres h e n t r y s e l f h l l l l h x l h l h h h x self refres h self refres h exit l h h x x x x i d l e p o w e r d o w n e n t r y h l x x x x x powe r do wn powe r do wn e x i t l h x x x x x rem a r k h = high level, l = low level, x = high o r l o w level (don 't care ) 10/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m 3. operative command t a ble cur r e n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop l h h h x n o p nop l h h l x t e r m nop l h l x ba/ ca/ a 10 re ad/w rit / bw illegal (n ot e 1) l l h h ba/ r a a c t bank a c tive,latch ra l l h l ba, a 1 0 pr e/pr e a nop (no t e 3) l l l h x ref a auto refres h (note 4 ) idle l l l l op-code, mode-add mrs mode regi ster h x x x x de s l nop l h h h x n o p nop l h h l ba/ ca/ a 10 read/r ead a begin re ad,l a tch ca, determine a u t o-precharge l h l l ba/ ca/ a 10 writ/writ a begin write,l a tch ca, determine a u t o-precharge l l h h ba/ r a a c t illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a precharge/prech a rg e all l l l h x ref a illegal ro w active l l l l op-code, mode-add mrs illegal h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l x t e r m t e rminal b u rst l h l h ba/ ca/ a 10 read/r ead a t e rminate b u rst,latch ca, begin ne w re ad, determine au to-precharge l l h h ba/ r a a c t illegal (n ot e 1) l l h l ba, a 1 0 pr e/pr e a t e rminate b u rst, prech a re l l l h x ref a illegal read l l l l op-code, mode-add mrs illegal h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l x t e r m illegal l h l h ba/ ca/ a 10 read/r ead a t e rminate b u rst with dm =?h?,lat ch ca,begin re a d ,determine auto-p r e c h a rge (note 2) l h l l ba/ ca/ a 10 writ/writ a t e rminate b u rst,latch ca,begin new write, de termine auto-p r e c h a rge (note 2) l l h h ba/ r a a c t illegal (n ot e 1) l l h l ba, a 1 0 pr e/pr e a t e rminate burs t with dm= ? h?, precharge l l l h x ref a illegal wr i t e l l l l op-code, m r s illegal 1 1 /20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m 3. operative command t a ble (continued) cur r e n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l ba/ ca/ a 10 t e r m illegal l h l x ba/ r a re ad/w rit e illegal (n ot e 1) l l h h ba/ a 1 0 a c t illegal (n ot e 1) l l h l x pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal read w i th ap l l l l op-code, mode-add mrs illegal h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l x t e r m illegal l h l x ba/ ca/ a 10 read/write illegal (n ot e 1) l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal w r ite w i th ap l l l l op-code, mode-add mrs illegal h x x x x de s l nop(idle af ter t rp ) l h h h x n o p nop(idle af ter t rp ) l h h l x t e r m nop l h l x ba/ ca/ a 10 read/write illegal (n ot e 1) l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a nop(idle af ter t rp ) (no t e 3) l l l h x ref a illegal pre-charging l l l l op-code, mode-add mrs illegal h x x x x de s l nop( ro w a c tiv e af ter t rcd ) l h h h x n o p nop( ro w a c tiv e af ter t rcd ) l h h l x t e r m nop l h l x ba/ ca/ a 10 read/write illegal (n ot e 1) l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal ro w activating l l l l op-code, mode-add mrs illegal rem a r k h = high level, l = lo w level, x = high o r l o w level (don 't care ), ap = auto pre-cha r ge 12/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m 3. operative command t a ble (continued) curre n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop l h h h x n o p nop l h h l x t e r m nop l h l h ba/ ca/ a 10 r e a d illegal (no t e 1) l h l l ba/ ca/ a 10 writ/writ a ne w write, d e termin e ap l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal wr i t e recovering l l l l op-code, mode-add mrs illegal h x x x x de s l nop(idle af ter t rp ) l h h h x n o p nop(idle af ter t rp ) l h h l x t e r m nop l h l x ba/ ca/ a 10 read/w rit illegal l l h h ba/ r a act illegal l l h l ba/ a 1 0 pr e/pr e a nop(idle af ter t rp ) l l l h x ref a illegal refreshing l l l l op-code, mode-add mrs illegal rem a r k h = high level, l = lo w level, x = high o r l o w level (don 't care ), ap = auto pre-cha r ge not e 1: ille gal to ban k in spe c ified st ates; functio n may be legal in the ban k indicated by bank a ddre s s (ba), depe nding o n the st ate of that bank. not e 2: mu st satisfy bu s co ntention, bu s turn ar oun d, and/or write recove ry req u i r eme n t s . not e 3: nop to bank p r e c h a rgin g or in id le st ate.may pre c ha rg e ba nk indi cate d by ba. not e 4: ille gal of any bank i s not idle . 13/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m 4. command t r ut h t a ble for cke cke curre n t s t ate n-1 n /cs /r /c /w addr . action h x x x x x x inv a lid l h h x x x x exis t self-ref resh l h l h h h x exis t self-ref resh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x nop(maint a i n self refresh) h x x x x x x inv a lid l h h x x x x exis t power down l h l h h h x exis t power down l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal both bank precharge power do w n l l x x x x x nop(maint a in power down) h h x x x x x refer to func t i on true t able h l h x x x x enter po wer down mode (note 3 ) h l l h h h x enter po wer down mode (note 3 ) h l l h h l x illegal h l l h l x x illegal h l l l h h r a row ac tive/bank ac tive h l l l l h x enter self -ref r esh (note 3) h l l l l l o p-code mode regi ster access h l l l l l o p-code s pecial m ode registe r a c ce ss all banks idle l x x x x x x refer to c u rrent s t ate any s t ate oth er than listed ab ove h h x x x x x refer to com m and truth t a ble rem a r k : h = high level, l = low level, x = high o r l o w level (don 't care ) notes 1: af te r cke? s lo w to high tran siti on to exist sel f refresh mod e .and a time of t rc (min) has to be elap se af te r cke? s low to hig h tran sition to issue a n e w co mmand. notes 2: cke low to high transitio n is a synchrono us a s if rest art s in ternal cl ock. notes 3: p o wer do wn an d self refresh can be ente r e d only from the idle st ate of all banks. 14/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m m o de register definition m o de register set the mod e re gister stores t he dat a fo r co ntrolling the v a riou s op erating m ode s of dd r sd ram whic h cont ain s add ressing mo de, burst len g th, /cas lat ency , test mode, dll re set an d variou s vend or s specifi c opinio n s. the default s valu es of the regi ster i s not def ined, so th e mode regi ster must be writt en af ter emrs setting for pro per ddr sdram operatio n. the mode regi ster is written by asserti ng low on /cs, /ras, /cas, /we and ba0 ( the ddr s dram sho u l d be in all ba nk prec ha rge with cke alre ady high pri o r to writing into the mode regi ster . ) th e st a t e of t he address pin s a0-a 12 in the sam e cycle a s /cs, /ras, /cas, /we and ba0 going low is written in the mode register . t w o clo ck cy cle s are requ este d to compl e te the write ope ratio n in the mode registe r . the mode regi ster content s can be cha nge d usin g the sa me com m and and clo c k cy cle requi rem ent s durin g ope rati ng as lo ng a s all banks are in the idle st ate. the mod e regi ster i s d i vided into variou s fields depe nding o n functionality . the bu rst len g th use s a0-a2, addressi ng mode u s e s a3, /cas latency ( read latency from colum n a ddre s s ) u s e s a4 -a6. a7 is us ed fo r tes t mo de . a8 is us ed for ddr reset. a7 must be set to low for n o rmal m r s o peratio n. 15/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m address input for mode re gister set 16/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m burst t y pe (a3) burst le ngth a3 a2 a1 a0 sequential a ddre s sing interleave ad dre ssi ng x x x 0 0 1 0 1 2 x x x 1 1 0 1 0 x x 0 0 0 1 2 3 0 1 2 3 x x 0 1 1 2 3 0 1 0 3 2 x x 1 0 2 3 0 1 2 3 0 1 4 x x 1 1 3 0 1 2 3 2 1 0 x 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 x 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 x 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 x 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 x 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 x 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 x 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 1 1 12 1 3 14 15 0 1 2 3 4 5 6 7 8 9 10 1 1 12 1 3 14 15 0 0 0 1 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 1 5 0 1 0 3 2 5 4 7 6 9 8 1 1 10 13 1 2 15 14 0 0 1 0 2 3 4 5 6 7 8 9 1 0 1 1 12 13 1 4 15 0 1 2 3 0 1 6 7 4 5 1 0 1 1 8 9 14 15 1 2 13 0 0 1 1 3 4 5 6 7 8 9 10 1 1 12 13 14 15 0 1 2 3 2 1 0 7 6 5 4 1 1 10 9 8 15 1 4 1 3 12 0 1 0 0 4 5 6 7 8 9 10 1 1 12 13 14 15 0 1 2 3 4 5 6 7 0 1 2 3 1 2 13 14 15 8 9 1 0 1 1 0 1 0 1 5 6 7 8 9 10 1 1 1 2 13 14 15 0 1 2 3 4 5 4 7 6 1 0 3 2 1 3 12 15 14 9 8 1 1 10 0 1 1 0 6 7 8 9 10 1 1 12 13 14 15 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 4 15 12 13 1 0 1 1 8 9 0 1 1 1 7 8 9 10 1 1 12 1 3 14 15 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 1 5 14 13 12 1 1 10 9 8 1 0 0 0 8 9 10 1 1 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 0 1 2 3 4 5 6 7 1 0 0 1 9 10 1 1 12 1 3 14 15 0 1 2 3 4 5 6 7 8 9 8 1 1 10 13 12 15 14 1 0 3 2 5 4 7 6 1 0 1 0 10 1 1 12 13 14 1 5 0 1 2 3 4 5 6 7 8 9 10 1 1 8 9 14 15 12 13 2 3 0 1 6 7 4 5 1 0 1 1 1 1 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 1 1 10 9 8 15 14 13 12 3 2 1 0 7 6 5 4 1 1 0 0 12 13 14 15 0 1 2 3 4 5 6 7 8 9 1 0 1 1 12 13 14 15 8 9 10 1 1 4 5 6 7 0 1 2 3 1 1 0 1 13 14 15 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 12 15 14 9 8 1 1 10 5 4 7 6 1 0 3 2 1 1 1 0 14 15 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 12 13 10 1 1 8 9 6 7 4 5 2 3 0 1 16 1 1 1 1 15 0 1 2 3 4 5 6 7 8 9 10 1 1 12 1 3 14 15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 1 0 * page length is a function of i/o organi zation and col u mn add re ssi ng 17/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m extended m o de register set ( em rs ) the extende d mode regi ster is written b y asse rti ng lo w on /cs, /ras, /cas, /we and high o n ba1 ( the ddr sdram shoul d be in all ban k pre c harg e with cke already prior to writin g into the extended mod e regi ster . ) t h e st ate of add ress pin s a0 -a10 and ba1 in the same cycle a s /cs, /ras, /cas, and /we goin g low is written in the extend ed mode regi ster . th e mo d e regi ster con t ent s can be cha nge d usi n g the same comm and an d clock cy cle requi rem ent s durin g ope rati on as long a s all banks a r e in the idle st ate. a0 is used for dl l ena bl e or disable. high o n ba0 is used for e m rs. all the other ad dress pins except a0 and ba0 must be set to low for p r op er emrs op e r ation. 18/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m output drive s t rength the no rmal d r ive stre ngth got all output s is spe c ified to be l v -cmos. by s e ttin g emrs s p ecific p a rameter on a6 and a5 , driving ca p a bility of dat a output drive r s is sele cted. t e mperature compensated self-refresh tcsr cont rol l ed by prog ra mming in the extended mo de regi ste r (e mrs). the m e mory autom atically cha nge s the self-refre sh cycle by temperatu r e fluctu ations. partial array self refresh in emrs s e tting ,memory array s i z e to be refres hed du ring self-refresh o peration is prog ram m able in orde r to reduce power . dat a out s i de the defined area will not be re t a ined during self-refresh. 19/20
eor e x em42am3284lba jul. 2006 www .eor ex.c o m package description 20/20

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